Efficient microprocessors (MPUs) have come to rely on embedded dynamic random access memory (eDRAM) for some cache applications that require extremely dense memory. That is, the MPU often includes memory (i.e., eDRAM) on the same semiconductor chip for such applications as the L3 cache memory. The most compact DRAM cell is the one transistor, one capacitor cell. To insure that the memory is robust as well as compact requires a high value capacitor that can be implemented in a small space on the chip. For this reason eDRAM has come to use deep trench capacitors to complete the memory cell. A deep trench capacitor is a vertical element; high capacitance is achieved by increasing the size of the capacitor by extending into the semiconductor substrate rather than by spreading out on the surface of the substrate.
Deep trench capacitors that are formed early in the process of circuit fabrication suffer from the high thermal budget that is required during front end of the line (FEOL) processing. The high thermal budget comes from, for example, temperatures required for depositions and anneals. The high thermal budget leads to a degradation of quality of the capacitor dielectric, especially when the capacitor dielectric is a high dielectric constant (high-k) material. The degradation of the capacitor dielectric makes thicker dielectrics necessary in order to suppress leakage currents. The thicker dielectric, however, results in a lower capacitance per unit area which can only be compensated for by increasing the depth of the trench capacitor. Increasing the depth of the trench capacitor increases the aspect ratio (the ratio of depth to width) of the trench which, in turn, leads to processing difficulties such as difficult etching requirements. High aspect ratio etches can lead to severe defect and yield problems. Additionally, in conventional processing the connection between the inner electrode of the trench capacitor and the drain region of the associated memory cell transistor is made by a polycrystalline silicon strap. If the polycrystalline strap is implemented with the first level of polycrystalline silicon, the strap is less conductive than metal, and if the strap is implemented with the second level of polycrystalline silicon the effective resistance of the strap is compromised by a Schottky barrier that is created at a silicon-metal interface.
Accordingly, it is desirable to provide integrated circuits that include capacitance deep capacitors and to provide highly manufacturable methods for fabricating integrated circuits that include high capacitance deep trench capacitors. In addition, it is desirable to provide methods for fabricating integrated circuits that include a deep trench capacitor having a metal strap between a capacitor electrode and an associated transistor. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.